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Switched Capacitor Differential Amplifier

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aryajur

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If anybody has read Razavi's Switched capacitor Amplifier chapter, could they please explain to me the working of fig 12.46 amplifier. I have attached it below for your reference. I don't understand how will the circuit amplify.
Looks to me C1 is charged and then just put in parallel to C2??
 

At sampling phase, C1 samples the input charge, during the charge distribution phase, C1 and C2 share the sampled charge. Vout/Vin = C1/(C1+C2).

You can also do the charge conservation at node X and Y to get this. Let's say the analog ground is 0 (during sampling phase, X, Y and output are shorted. those potential is 0).
At phase1: Qc1=-C1*Vinp; Qc1'=-C1*Vinm; Qc2 =0 and Qc2'=0
At phase2: Qc1=C1*[Vx-Vop]; Qc1'=C1*[Vy-Vom]; Qc2=C2*[Vx-Vop]; Qc2'=C2*[Vy-Vom]
(Note the positive node of the capacitor is on the side of the floating node X,Y)
Charge conservation: Delta_Qc1 + Delta_Qc2=0.
At node X: (C1+C2)*Vx - (C1+C2)*Vop + C1*Vinp=0
At node Y: (C1+C2)*Vy - (C1+C2)*Vom + C1*Vinm=0
Take the difference of these equation, we got (C1+C2)*Vo=C1*Vin.
 
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    cxtdyl

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Yes thats what I meant that the capacitors get in parallel and the gain is actually less than 1! But in Razavi this is given as a non inverting amplifier - he first introduces a switched capacitor non inverting amplifier (non differential) with a gain of C1/C2 then he says the differential implementation of this amplifier is this (the image I attached). So I don't see how its gain can be C1/C2 or similar, i.e. have a possibility to be >1
 

some ASIC design use parastic Cap for
switch Cap amplifier ..

Like flash A/D comparator
 

Not quite the same question, but I could use some basic understanding of the parasitic-insensitive switched cap shown in just about every circuit I've seen documented. If a positive input voltage is applied and placed across the sample capacitor in the first phase, then in the second phase the resulting voltage on the opamp side of the sampling capacitor is negative.

For my design I do not have +/- voltages, so a negative input voltage is not even in the acceptable input range of the design. Any suggestions? Since all the documents I've found seem to use this arrangement it must work, but how...
 

Good to find this thread. I simulated the circuit and the attenuation follows c1/(c1+c2) equation.
 

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