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  1. #1
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    anyone have ROM design code in VERILOG......

    hello folks.........

    the use of package in VHDL cannot be used in Verilog...

    so does anyone have idea or code of a simple ROM design........in VERILOG

    thanks

    •   Alt27th November 2006, 14:07

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    anyone have ROM design code in VERILOG......

    module ROM_Module (clk, reset, cs, rd, address, data_out)
    begin
    input clk;
    input reset;
    input cs;
    input rd;
    input [7:0] address;
    output [7:0] data_out;

    reg [7:0] data_out;

    reg [7:0] ROM[0:255];

    always @(posedge clk or negedge reset)
    begin
    if(~reset) begin
    ROM[0] <= 8'b0000_0000;
    ROM[1] <= 8'b0110_0111;
    //..................complete ROM init
    end
    else if(~cs & ~rd)
    data_out <= ROM[address];
    else
    data_out <= 8'hZZ;
    end module


    It will be something like that. For more implementations you can refer to XST help which includes a lot of implementations for ROMs, RAMs,....

    Best Wishes



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    Re: anyone have ROM design code in VERILOG......

    Thanks for that Yaseer...

    but i need to know any example code if you have

    plz post it...............


    thanks


    and what does this XST help refer to..............



    •   Alt27th November 2006, 14:53

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    Re: anyone have ROM design code in VERILOG......

    Rakesh,
    [
    quote="rakesh_aadhimoolam"]hello folks.........

    the use of package in VHDL cannot be used in Verilog...
    [/quote]

    SystemVerilog has this.

    so does anyone have idea or code of a simple ROM design........in VERILOG

    thanks
    Not clear how does it tie to having/not having a package at the first place. A simple memory is implemented using:

    reg [31:0] my_rom [0:1023];

    Whether it is a ROM or RAM depends on your model. ALso look at web sites like Micron, there are several Verilog beh models available.

    HTH
    Ajeetha, CVC
    www.noveldv.com



    •   Alt27th November 2006, 15:18

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    Re: anyone have ROM design code in VERILOG......

    can anyone give me the whole code of DATA PATH including RAM, ROM, PC, ALU, MUX, instruction register etc and CONTROL PATH



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    anyone have ROM design code in VERILOG......

    Hi kanza, Are you looking for HDL code of a CPU?
    Try browsing this collection of free CPU cores:
    http://www.opencores.org/browse.cgi/...microprocessor



    •   Alt16th May 2007, 08:45

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    Need verilog code of state machine control for the datapath

    no...actually m doin ASIC project on 2051(microcontroller) core... needed a verilog code of complete data path includin ROM RAM Program counter multiplexers ALU control path......

    Added after 1 hours 7 minutes:

    Added after 3 minutes:

    I am doing an ASIC project on 2051(micro-controller) core..i want verilog code of state machine control for the datapath...the instructions are ADD,SUBB,OR,XOR,NOR,RR,RL,SWAP,INC,DEC,MOV,XCH,NOP ,CPL,CLR,RET.

    Can anyone help me out..its urgent



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    Re: anyone have ROM design code in VERILOG......

    I take this code in xilinx papers I hope it can help you.
    /*
    * ROM_RTL.V
    * Behavioral Example of 16x4 ROM
    */
    module rom_rtl(ADDR, DATA) ;
    input [3:0] ADDR ;
    output [3:0] DATA ;
    reg [3:0] DATA ;
    // A memory is implemented
    // using a case statement
    always @(ADDR)
    begin
    case (ADDR)
    4'b0000 : DATA = 4'b0000 ;
    4'b0001 : DATA = 4'b0001 ;
    4'b0010 : DATA = 4'b0010 ;
    4'b0011 : DATA = 4'b0100 ;
    4'b0100 : DATA = 4'b1000 ;
    4'b0101 : DATA = 4'b1000 ;
    4'b0110 : DATA = 4'b1100 ;
    4'b0111 : DATA = 4'b1010 ;
    4'b1000 : DATA = 4'b1001 ;
    4'b1001 : DATA = 4'b1001 ;
    4'b1010 : DATA = 4'b1010 ;
    4'b1011 : DATA = 4'b1100 ;
    4'b1100 : DATA = 4'b1001 ;
    4'b1101 : DATA = 4'b1001 ;
    4'b1110 : DATA = 4'b1101 ;
    4'b1111 : DATA = 4'b1111 ;
    endcase
    end
    endmodule



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    Re: anyone have ROM design code in VERILOG......

    Quote Originally Posted by mmoctar
    I take this code in xilinx papers I hope it can help you.
    /*
    * ROM_RTL.V
    * Behavioral Example of 16x4 ROM
    */
    module rom_rtl(ADDR, DATA) ;
    input [3:0] ADDR ;
    output [3:0] DATA ;
    reg [3:0] DATA ;
    // A memory is implemented
    // using a case statement
    always @(ADDR)
    begin
    case (ADDR)
    4'b0000 : DATA = 4'b0000 ;
    4'b0001 : DATA = 4'b0001 ;
    4'b0010 : DATA = 4'b0010 ;
    4'b0011 : DATA = 4'b0100 ;
    4'b0100 : DATA = 4'b1000 ;
    4'b0101 : DATA = 4'b1000 ;
    4'b0110 : DATA = 4'b1100 ;
    4'b0111 : DATA = 4'b1010 ;
    4'b1000 : DATA = 4'b1001 ;
    4'b1001 : DATA = 4'b1001 ;
    4'b1010 : DATA = 4'b1010 ;
    4'b1011 : DATA = 4'b1100 ;
    4'b1100 : DATA = 4'b1001 ;
    4'b1101 : DATA = 4'b1001 ;
    4'b1110 : DATA = 4'b1101 ;
    4'b1111 : DATA = 4'b1111 ;
    endcase
    end
    endmodule
    no default case??
    will thr be any prob?
    Shiv



  10. #10
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    anyone have ROM design code in VERILOG......

    All 16 input values are specified, so the example will work fine without a default case.
    However, I usually include "default: DATA = 4'bxxxx;" to help catch other bugs during simulation (such as ADDR undefined).



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