flysnows
Junior Member level 2
Thesis: An 8Bit 150MHz CMOS AD Converter
This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC
that performs analog processing only by means of open-loop circuits such as
differential pairs and source followers, thereby achieving a high conversion rate.
The concept of “sliding interpolation” is proposed to obviate the need for a large
number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining incorporates distributed sampling between the stages so
as to relax the linearity-speed trade-offs in the sample-and-hold functions. This
work also introduces a “clock edge reassignment” technique that suppresses timing
mismatch issues in interleaved systems. Moreover, in order to reduce the integral
nonlinearity error (INL) with negligible speed or power penalty, a “reinterpolation”
method is proposed.
This dissertation presents an 8-bit, 5-stage interleaved and pipelined ADC
that performs analog processing only by means of open-loop circuits such as
differential pairs and source followers, thereby achieving a high conversion rate.
The concept of “sliding interpolation” is proposed to obviate the need for a large
number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining incorporates distributed sampling between the stages so
as to relax the linearity-speed trade-offs in the sample-and-hold functions. This
work also introduces a “clock edge reassignment” technique that suppresses timing
mismatch issues in interleaved systems. Moreover, in order to reduce the integral
nonlinearity error (INL) with negligible speed or power penalty, a “reinterpolation”
method is proposed.