Verilog-modified 3to8 decoder...wrong?

verilog decoder schemantic

hi all,
i'm actually doing a project that includes the 3-8 decoder. while some of u think a 3-8 decoder has a simple schematic with the standard truth table, which is:



the schematic should be like:



-----
now, what if the truth table is like this?



the idea is to turn on multiple-same-capacitance value at the same time to have a bigger capacitance. so that, the layout person won't have to create different value of capacitance. thus, only 1 standard capacitance value is created.

ok then, since i have problem to generate the schematic out from the truth table manually, i have to use verilog code and let the Synopsis software to generate the schematic for me. and so, let's say the input is, is this the correct verilog code????

module decoder (sel,y);
input [0:2] sel;
output [0:7] y;
reg [0:7] y;
always @ (sel)
begin: decode
case (sel)
3'b000: y=8'b00000001;
3'b001: y=8'b00000011;
3'b010: y=8'b00000111;
3'b011: y=8'b00001111;
3'b100: y=8'b00011111;
3'b101: y=8'b00111111;
3'b110: y=8'b01111111;
3'b111: y=8'b11111111;
default: y=8'bxxxxxxxx;
endcase
end
endmodule

i've tried the code and the output is as followed:



isn't quite weird? only 6 outputs...i'm expecting 8 outputs.... my friend told me the synopsis already optimize the circuit to a simpler version!
How's that? is it true then?

pls help. Thanks in advance...

p/s: i'm not used to verilog and Synopsis... only small part of the project uses digital parts...

verilog decoder

In order to look at schematic, you probabily invoked 'design analyser' (da) tool. Firstly the tool is bug ridden and is not supported completely (in the sense that bugs in the schematic viewer are a low priority for the company). This is because synthesis / asic designers rarely rely on the schematics.

Having said this, I see in the schematic, the output is correct in the number of bits --- y[0:7]. Notice that there is a blue line from select bus to the output. This is supplying the additional bits to the 6 output bits (in green) you are seeing (athough I have not checked for logic correctness yet).

When using synthesis tool always look at the output netlist (writen by the tool in verilog), not at the schematic for correctness.

3-8 decoder verilog

The schematics seem to be correct. But it is always advisible to check the gate-level netlist after the systhesis step. I don't know about the bugs in Design Analyzer as I do not use it very frequently.