# how to go Binary addition in vhdl with vectors

Hi Guys

Can anyone pls tell me how to do binary addition with vectors...
i tried to do but it gives me a error as "Type error resolving infix expression "+" as type std_logic_vector."
```Code VHDL - [expand]1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Library IEEE;
Use Ieee.std_logic_1164.all;

Port(
a: in std_logic_vector(3 downto 0)  ;
sum:out std_logic_vector(3 downto 0)
);

signal tmp : std_logic_vector(3 downto 0);
begin

tmp <= a(0) + a(1) +a(2) + a(3) when en = '1' else "0000";
sum <= tmp;

end behav;```

•

Hi!
1. Use Ieee.std_logic_unsigned.all;
2. en: in std_logic;
3. you have to extend a(0), a(1) etc to 4bit by "000"&

Have a nice day!

Code:
```Library IEEE;
Use Ieee.std_logic_1164.all;
Use Ieee.std_logic_unsigned.all;

Port(
a: in std_logic_vector(3 downto 0) ;
en: in std_logic;
sum:out std_logic_vector(3 downto 0)
);

signal tmp : std_logic_vector(3 downto 0);
begin

tmp <= (("000"&a(0)) + ("000"&a(1))+ ("000"&a(2)) + ("000"&a(3))) when en = '1' else "0000";
sum <= tmp;

end behav;```
[/code]

Originally Posted by dunets
Hi!
1. Use Ieee.std_logic_unsigned.all;
2. en: in std_logic;
3. you have to extend a(0), a(1) etc to 4bit by "000"&

Have a nice day!

Code:
```Library IEEE;
Use Ieee.std_logic_1164.all;
Use Ieee.std_logic_unsigned.all;

Port(
a: in std_logic_vector(3 downto 0) ;
en: in std_logic;
sum:out std_logic_vector(3 downto 0)
);

signal tmp : std_logic_vector(3 downto 0);
begin

tmp <= (("000"&a(0)) + ("000"&a(1))+ ("000"&a(2)) + ("000"&a(3))) when en = '1' else "0000";
sum <= tmp;

end behav;```
[/code]
Hi Dunets
Thanks a lot for your help.
tama

•

Originally Posted by s3034585
Hi Guys

Can anyone pls tell me how to do binary addition with vectors...
i tried to do but it gives me a error as "Type error resolving infix expression "+" as type std_logic_vector."

Library IEEE;
Use Ieee.std_logic_1164.all;

Port(
a: in std_logic_vector(3 downto 0) ;
sum:out std_logic_vector(3 downto 0)
);

signal tmp : std_logic_vector(3 downto 0);
begin

tmp <= a(0) + a(1) +a(2) + a(3) when en = '1' else "0000";
sum <= tmp;

end behav;

include the foolowing libraries
arith and unsigned too then they will executed

i prefer the numeric lib instead of arth lib, the latter is synopsys prepoerity.

6. ## Re: how to go Binary addition in vhdl with vectors

can someone please explain to me what this does ("0000"&a(0)) in this particular line of text below. the exact code is in one of the replies on this thread

Code:
```tmp <= (("000"&a(0)) + ("000"&a(1))+ ("000"&a(2)) + ("000"&a(3))) when en = '1' else "0000";
sum <= tmp;```

•

7. ## Re: how to go Binary addition in vhdl with vectors

It creates a vector. a(0) is a single bit. Only vectors of type signed or unsigned can be added together.

8. ## Re: how to go Binary addition in vhdl with vectors

The code calculates the number of '1' bits in input vector a. Is this what you want to achieve?

The question title might suggest that you want to add multiple vectors. But there's only one input vector.

--[[ ]]--