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radix-4 decimation in frequency fft

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siva_7517

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radix-4 fft improvement

Dear frens,

I am currently involve in asic design for designing a FFT radix-2 and radix-4 butterfly structure. I have done both design using verilog code. Eventually, i need to do some modification (improvement) on the design as a contribution to my postgraduate studies. Can anyone suggest to me any modification that can be done to the radix-4 fft, so that it can have better performance . Thanks in advance.

Regards,
Siva
 

radix-4 fft improvement

can u post a diagram of how u have implemented the butterfly structure types of multipliers used etc
 

Re: radix-4 fft improvement

Dear Fren,

I have attached the butterfly structure of radix-4 for your kind review.
I have design the design using this butterfly structure.

Regards,
Siva
 

radix-4 fft improvement

o.k
u have a parallel implementation.
u have a lot of mul's and adders right.
why not serialize this??
this would be a good one if u can serialize and wat
type of multipliers and adders have u used.wat
speed have u obtained after synthesis.
 

Re: radix-4 fft improvement

Hi,

Thanks for the reply. My speed for this design is 50MHz. I have used behavioral verilog to do the coding. I am a bit blur on how to implement it in serial. Hope u can give me some guideline on this. Thanks in advance.

Siva
 

Query

hi..

Wel i saw one of yours post wherein u spoke about OFDM..
can u pls help me about the same..
Expectng your fruitful reply..

With Regards
Harsha
 

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