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hirarchy flattening error in cadence spectre simulations

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cadence error too many terminals given

I am getting following error in cadence and don't have a clue as to how to fix it.
does anybody know what is it exactly ?

Error found by spectre in 'bandgap':'I14' during hierarchy flattening.
I14.I42.Q1: too many terminals given (12 > 4)

thanks

Sachin
 

spectre hierarchy flattening

u have an instance called I14.I42.Q1 check its connections
 

thats the vertical pnp transistor in bandgap reference circuit. I checled the connections and everything is perfectly ok with the connections/terminals.
 

Hello,

I have a similar problem with a Verilog-A based model of FET. The number of terminals is correct, but I am getting a an error of "too many terminals given" nature.

Any ideas?
 

Hello every body,

I am recieving the same error while simulating my circuit containing Mosfets in Cadence IC design tool.

"Too many terminals given"

What would you recomment me to do??
 

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