blowfish
Member level 4
Could any one help me in the designing of digital controlled delay unit circuit for my Delay Locked loop Circuit
As i am not able to implement uisng a Verilog Simulation tool ,FPGA ADVANTAGE PRO.
Send me any ALL DIGITAL DELAY LOCKED LOOP CIRCUIT ,as i am not able to find any complete circuit in the internet or books .
Also how to implement "Hiearchial delay unit" (HDU) shown in this paper attached.
As i am not able to implement uisng a Verilog Simulation tool ,FPGA ADVANTAGE PRO.
Send me any ALL DIGITAL DELAY LOCKED LOOP CIRCUIT ,as i am not able to find any complete circuit in the internet or books .
Also how to implement "Hiearchial delay unit" (HDU) shown in this paper attached.