Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What are the different methodology to fix CTS skew issue?

Status
Not open for further replies.

saroj_123

Newbie level 2
Joined
Sep 8, 2006
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,296
Hi,
I am using soc for backend flow.I have few Queries regarding CTS.
-- What are the different methodology to fix CTS skew issue?
-- How SOC is doing CTS ?
If anyone having good doc about CTS please send.
Thanks
 

Re: What are the different methodology to fix CTS skew issu

Some of the things you can do are . . .
- Rebuffering the clock trees
- Balance Clock Trees (either rebuffering or by routing)
- Try playing with Useful skew

--
ay
 

Re: What are the different methodology to fix CTS skew issu

How much is your insertion delay settings.
 

Re: What are the different methodology to fix CTS skew issu

CTS minimises skew by adding buffers in the clock path in the appropriate location. The goal is minimise the skew by adding minimum number of buffers.
 

Re: What are the different methodology to fix CTS skew issu

The CTS is an main process of BE tools. In normally, CTS content two main step: clock tree routing and clock bufferring. To minimize clock skew, we should separate clock pins into the clock-group. The clock-group is a set of clock pins that have the same clock source and are so small to build clock tree with minimize clock buffer.

+ There are two kind of clock-tree styles: H-tree and clustering tree. Now, the clustering tree is more optimized structure then H-tree. For more information about H-tree and clustering, please refer to google. [:)]

+ However, you're had not to divide the large pin group into a couple of small pin group.
It will take more buffer for hold time fixing. Or It will take your chip fail because of mixed clock paths (difference clock between captured path and launch path).[/b][/code]
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top