buenos
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hi.
i have tried to simulate the post fit vhdl model in the modelsim, started from the xilinx-ISE for a Coolrunner2 CPLD, but it has an error:
in the modelsim:
...
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./TCTest.tdo PAUSED at line 9
in the file, line 9:
vsim -t 100ps -sdfmax /UUT=toptt_timesim.sdf -lib work TCTest
If I try to simulate the behavioral model, then it works fine.
i have tried to simulate the post fit vhdl model in the modelsim, started from the xilinx-ISE for a Coolrunner2 CPLD, but it has an error:
in the modelsim:
...
# Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./TCTest.tdo PAUSED at line 9
in the file, line 9:
vsim -t 100ps -sdfmax /UUT=toptt_timesim.sdf -lib work TCTest
If I try to simulate the behavioral model, then it works fine.
