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Formal Logic Equivalent Check (LEC)

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davyzhu

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logical equivalence check

Hi all,

When do Formal Equivalent Check (RTL and Gate Level) , I remember that the tool compare the comb logic between D-FF .

But when synthesis use re-timing and gated clock, can LEC tool compare
RTL and Gate?

And is gated clock one form of re-timing?

I am reading a paper from SNUG about gated clock (How to successfully
use gated clock...) but I cannot understand the waveform...

Best regards,
Davy
 

logic equivalence check

davyzhu said:
Hi all,

And is gated clock one form of re-timing?

I am reading a paper from SNUG about gated clock (How to successfully
use gated clock...) but I cannot understand the waveform...

Best regards,
Davy
Click to expand...

Gated clock is not a form of re-timing, it is used for saving power.

Can you show your waveform, and explain detailedly.
 

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    davyzhu

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synopsys lec

in lec
set flatten model -gated_clock
will solve the problem
 

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    davyzhu

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formal equivalency check

synopsys dc
formality
 

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    davyzhu

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logic equivalent

hi all,

if u r using the synopsys DC and formality.the DC will give the SVF file as output while doing the synthesis.which will give the gudence to the formality.so that the logical equvalency for the rtl vs netlist will pass.


regards,
rameshs
 

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    davyzhu

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logic equivilant to exclusive -or gate

HOw about design with ICG cells ?? like ICG cells from artisan ... ??
 

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