Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

A DMT-based VDSL receiver front-end design in 0.35μ

Status
Not open for further replies.
B

benever

Member level 5
Joined
Oct 5, 2006
Messages
90
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,871
Abstract
A VDSL receiver front-end with a programmable
gain low noise amplifier is presented. The amplifier
consumes only 35mW from a 3.3V supply in a
0.35μm BiCMOS technology and is suitable for
DMT-based VDSL systems with bandwidths up to
12MHz. The linearity is expressed in Missing Band
Depth (MBD) for a worst case bandplan . The LNA
uses an inverting architecture and has a constant
input impedance. A technique was used to suppress
the distortion caused by the switches in the signal
path. The area is only 0.2mm2.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top