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When to remove false path/dont touch on reset nets?

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design_engineer

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dont_touch_network reset

During synthesis, we apply a dont_touch_network and false_path on the reset ports because they will be buffered using CTS in the P&R. When should we remove these constraints - at entry into the P&R tool or after floorplanning/placement and before CTS?
 

remove false path

Generally buffering of nets in layout is refered to as high-fanout-net synthesis rather than CTS. The answer to your question is: remove the two constraints AFTER high-fanout-net synthesis
 

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