about distribute voltage or current in a large chip??

hello!!

How do we distribute voltage or current references in a large chip?

design a ldo or dc-dc

First, your question is very tricky as you have a LARGE chip.
For a large chip, you may have multiple VDD/VSS.
Then for each pair VDD/VSS, you put your blocks close to that pair and route power/ground signals to those blocks. For example, PLL use PLLVDD/PLLVSS.
However, for stable output with low noise and high PSRR, you may need a seperate LDO/DC-DC converter for each power pair in order to form a power management system on a LARGE chip.
Current on the other hand can be generated from BANDGAP that already have in LDO or from PTAT current mirrors. Don't try to flush bias voltage from current mirrors to all other blocks that scatter around the chip and that way, you will lose voltage margin as there is R drop across signal lines. Always flush current instead of voltage and regenerate the voltage right inside the necessary block to create final biasing. Since for LARGE chip, you cannot have a single current generator, separate each bias generator that close to your necessary blocks to minimize noise coupling across the chip.