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How to generate clock in digital circuits and what's technology file for netlist?

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vsrpkumar

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1)what is technology file for netlist.what are differences between technology files between FPGA(altera) and asic
2)How to generate clock in digital circuits(help of logic design)
 

Re: query in netlist

just use ring osilltor to generate the clock
the difference will be only at GDS format
 

Re: query in netlist

hi,
1. please clarify more clearly no 1. questions.
2. using logic to generate fast clock? you can use delay cell to delay a clock and then XOR the origin clock and delayed clock. but be careful do that becoz it's need more design exprience.
 

Re: query in netlist

Here The technology library depends on the fab which ur going to fabricate a chip with perticular micron technology,and process dependent.

Library in the sense all components inthe lib are predesigned and charecterised(semicustom).

In case of altera library, its a FPGA library exa: in ALTERA STRARTIXII all the cell info is defined in a stratixII library.

The cell (LUT's & FLOPS) characteristics cant be changed,only routing will effect the design.


---satya
 

Re: query in netlist

How to generate clock ...

Use the crystal oscillator
p.s.
It not resonator !!!
Its a circuit with levels CMOS or TTL.
 

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