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The status at Cadence about VAMS software

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eda4you

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in my company we worked about 2 man-years for modeling a complex soc system. as larger the system get the more fault and netlist errors occured, although the blocks work fine, but simulating the whole system is unimpossible! the design support helped us, but what made me wundering is that the vams software development has been put on 'ice". So my question is: has sombody information about the real status at cadence or is vams dead?

thx for insider information
 

Re: Cadence and vams

Hello !!!

I may say following =>
We designed the ROM 16Kx16. It is a very big circuit.
I did the extract from the layout and simulate one row in layout , it did ~2 weeks.

We made extract from layout and all transistors had changed on verilog model. The simulation been go in LDV. Simulation been make ~ 1 hour.

We verified only accuracy of connections !!!
 

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