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phase margin of phase lock loop

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surianova

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hi all!

How to check the phase margin of phase lock loop? The input is the frequncy, and how to do the AC analysis in Spectra ?
 

u have to do a small signal model in s-domain
 

phase margin can be estimate by the step response of vco's bias
 

Normaly the pahse margin is only computed for a linear model of the pll. as mentioned before a step response of the loop filter gives the correct answer. i am sure you will find in literature the equation where you can e.g. compute the phase margin with the first two overswing amplitudes.
 

is it mean i can't straight away get the result from my schematic or transistor level using Iprobe from candence?
 

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