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Help, Which structure is right(ESD protect circuit)?

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sophiefans

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ESD protect circuit layout

Which one is right?
(A) is mentioned in design-rule. SAB covers poly region
(B) comes from certain practice ESD protect circuit layout. SAB covers Drain region.

Which one do you think is right?
thanks a lot.

**broken link removed**
 

(A) is right.
Salicide block supresses the low-resistance layer that reduces source-drain resistance at the surface. In ESD protection one wants the current o spread thru the bulk/depth of the drain and source, because it'll dissipate heat better, and, most important, will do this as far as possible from the thin oxide of the gate/channel interface.
In (B) the ESD current will come back to the surface as soon as the salicide is available (lowest resistance path).
 

thanks, i'v got it.

but, the layout drawn as (A) can't be extracted out any mos FET just because of SAB. then, What i should do to extracted mos FET out?
 

Design kit must have a special rule (and layer) to either ignore ESD protection
ggmos or to extract it in a "special" way. ESD protection structures are very specialised and are usually extracted only by the foundry, which supply the cells and ready made netlists for LVS and simulation. Because of this many design kits do not include rules for ESD extraction, since the simulation results that can be obtained may not accurately model the behavior of the circuit.
 

    S

    sophiefans

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Oh, my god.
In this case, I have to promise that i 've understood all the rules correctly. The words in green font is from design-rule. This rule does not mention NMOS used as IO protect circuit. Then, does it mean that i should use SAB to cover all the region of an NMOS In IO protect circuit? I mean why this rule does not mention NMOS in IO protect circuit?

Salicide blocking mask on ESD IO protection circuit :
PMOS & ESD implanted NMOS IO buffers should not have salicide formed at the regions close to the Poly gate.
 

i made the same experience. the problem within layout (a) is that you have to ignore the drc errors. Normaly you can help yourself in setting a rectangel above the device with drc ignore. that is the way i dit it. but to be sure you should contact your device or process engineers.
 

Then, does it mean that i should use SAB to cover all the region of an NMOS In IO protect circuit?
Click to expand...
Just as Fig (A) demonstrates.
I mean why this rule does not mention NMOS in IO protect circuit?
Click to expand...
I think "ESD implanted NMOS IO buffers" include "NMOS in IO protection circuits"
 

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    sophiefans

    Points: 2
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I think "ESD implanted NMOS IO buffers" include "NMOS in IO protection circuits"
I will do like this.


By the way, does the scribe line guard ring should use PAD layer? Why?
thanks
 

Yes. The PAD layer should be included in the scribe line. Because PAD layer ususlly defines where the passivation will be etched away. Removing the passivation layer in the scribe line helps dicing.
 

in(B) then case , contact and sab is right?
 

A is right

as i know, SAB layer is used to block the salicide process, salicide nmos can't using for ESD protection, because it's low-resistance and bird-peak structure...

i'm not sure....
 

Unless ur design is not following foundry type esd design, do not ignore DRC violations for esd. Esd rules will be checked if you put the required esd checking layer.
 

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