Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

2stage op amp problem?

Status
Not open for further replies.

spbhu

Member level 2
Joined
Dec 5, 2005
Messages
42
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,601
I have a question which is very important in pracitcal design, i.e.
for a 2 stage op-design, how do you manage the power ? How much current
need to be put into the first stage and how much to the 2nd stage in order
to achieve an optimum performance? What are the considerations? Is
there any material or paper make discussions about this?

Thanks very much...
 

I think the 2 stage power is decided by the loading of OPA. Then you can design 1 stage by 2 stage loading. This is only one thought, I think there may be other different opinion on different situation.
 

Hi,
The power dissipation dependss on the supply voltage and the current Iss.

Iss itself depends on Slew rate . Slew rate depends on the output capacitance and the output capaitance depends on the Bandwidth.

So you can see that power disspation depends on many factors. Depnding on all the specs you can design your system.

thanks
sarfraz
 

I mentioned that most the text book use the slew rate specification to manage the first stage current, however, if for applications where slew rate is not provided, (e.g. a filter design may not provide the slew rate spec's), then how do you manage the 2 stage current consumption for a given Vdd, and maximum power limit?
Thanks
 

Hi,
For any design you might be provided with the maximum power disspation.

Now

Power Dissipation = (Vdd + |Vss|)* Iss

From this you can get the maximum value for Iss.

Is there any other concern?

thanks
sarfraz
 

The current of the first stage should be smaller because you would get higher gain(higher mos output resístance ro). However, it should be not too small because of Slew Rate.
The current of the secound stage should be higher because of easier Miller compensation (gm is higher, Cm smaler), and higher output current .
 

If the opamp is designed as buffers for Reference voltage, then speed requirement or slew rate is not important. You may design 1st stage and 2nd stage will minimum possible current, eg 5uA to 10uA, as long as it is >> 100 time of the process leakage current.

If the opamp inputs are AC, then you need to consider slew rate. Increase current until you meet slew rate requirement.

To drive a big cap load, normally you have to add additional buffer stage after the 2nd gain stage. Withough buffer stage, the cap load will affect opamp frequency response. Yet, the 1st and 2nd stage current is still depends on slew rate, increase the current at buffer stage only if you need to provide drive capability.

Hope this helps.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top