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Hi,
clock synthesis is a vast subject. It can be seen from many perspectives i.e.
clock synthesis in FPGA
clock synthesis in ASICs
clock synthesis in different technologies for FPGAs and ASICs
clock synthesis is basically the formation of optimised and skewless clock tree in the design. There are various back-end tools those are used to do this tedious task.
here is a link. try to go through the content. It will give you some insight into the subject.
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