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how can i divide the clock by 3

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kinjal_book

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hi
can anyone help me in dividing the clock by 3 and with positive edge trigger FF and with 50% duty cycle...also area should be minimum..
 

This is a classic problem... But first we need more info:

What kind of FF? (J-K, Toggle, D-gates)
Do they have set/reset?

One way of implementing this with half the flip-flops is to have an asynchronous reset. Is a brief glitch allowed (i.e. can you implement a glitch filter) ?
 

This is a classic interview quiz.

The two-bit D flip-flops Q[1:0] are counting like this way "00 01 10" repeatively.
D[1:0] are the data inputs of the flip-flops Q[1:0].
D[0]= ~Q[1] & ~Q[0];
D[1]= ~Q[1] & Q[0];

another D flop-flop HCDLY is clocked by the inverted clock to shift Q[0] for half clock cycle.

the final 50% duty cylce with no glith & minimum area = Q[0] | HCDLY
 

Please try to find the same topci in this forum. This question is discussed many times.
 

kinjal_book said:
hi
can anyone help me in dividing the clock by 3 and with positive edge trigger FF and with 50% duty cycle...also area should be minimum..
Click to expand...


i hope this may be useful..

see this link
 

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