Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The maximum time is governed by the setup time equation and the minimum time is defined by the hold time equation. If you don't know the way to analyse for setup time and hold time analysis let me know. I'll write up that stuff and attach it. Make sure you put it as personal message least I miss this post.
Considerer two flip flops (FF1 and FF2) that have logic stuff between them (AND, OR etc..)
You need to be sure that you garantee the:
Short path condition
ζQm1 + ζPm > ζH2 + ζC
Where Q index refers to the FF 1 delay, m to the minimum, ζPm refers to the delay caused by the logic stuff between the two flip flops, ζH is the hold time of FF2 , ζC is the clock skew.
For the long path condition you have:
ζQM1 + ζPM + ζS < ζTw - ζC
where ζS is the setup time of FF1 and ζTw is the clock pulse width
well, it depends on whether you've hold time constrain in multi-cycle path.
1. if you have "set_multicycle_path -hold" for more than one cycle, than the circuit has max time limit;
2. otherwise, the circuit can run whatever speed below the max frequency.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
