How do we protect Verilog/VHDL IP cores?

xstal · Oct 12, 2006

Hi all,

I would be very grateful to anyone who can throw light on this
topic.

How do we protect Verilog/VHDL IP ? Meaning , we do not want to give
source code to our customers

Is there a standard binary format to which we could convert ? Is this
standard format compatible with other simulators ? How do other
companies handle this ? Is there any free ware available to accomplish
this ? Please give me all the leads possible on this.

Thanks and regards

dunets · Oct 12, 2006

Re: IP CORES Protection

Hi!
Now, it not possible to protect your IP (VHDL, Verilog), but it will be soon: **broken link removed**

Sigma|Six · Oct 12, 2006

IP CORES Protection

Hi, if you do not want to give the HDL source code to your customer, just simply don't give to them.

If you affraid that someone will decode your IP from the BITSTREAM of the FPGA devices, may be you should look into this link, Altera does put some efford to this matter.

https://www.altera.com/products/devices/stratix2/features/security/st2-security.html

teja321 · Oct 16, 2006

Re: IP CORES Protection

How actually the xilinx and altera guys protect their cores. Is there any information on that?

whicun · Oct 16, 2006

Re: IP CORES Protection

You can complier your HDL source codes to EDIF.
EDIF file format should be recognised by many EDA tools.

the_penetrator · Oct 17, 2006

Re: IP CORES Protection

In the upcoming Accellera VHDL 2006 (version 3.0) standard, it will be possible to encrypt (via triple-DES at least i think) specific parts of the source code (marked via meta-comments).

the_penetrator

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How do we protect Verilog/VHDL IP cores?

xstal

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dunets

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Sigma|Six

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teja321

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whicun

Junior Member level 1

the_penetrator

Full Member level 5

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