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voltage doubler architecture consumes <50uA..

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gggould

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Hi all,

I want to design a charge pump which can provide 5V/less than 10uA output.
The supply is 2.9~4.6V, while the total current budget is 50uA.

Can someone suggest me a good charge pump architecture, which can fit in (or close to) my 50uA current budget? And how to partition power budget to individual block???

I tried to build one with bandgap/regulator/1MHz oscillator/voltage doubler(using the one proposed by WU and CHANG in JSSCC 04/1998), but the overall quasi current is > 500uA...

Thanks a lot and have a nice day...

gggould
 

most of the power is spend in the driver buffer circuit (crowbar current and parasitic capacitance resulted waste of power), otherwise approximately 20% efficiency goal of yours for a doubler is easily achiavable.

If power is not wasted by driver buffer but charge transfer section then capacitor and switch device sizings might not be optional.

If you are using dickson type charge pump diode VI drop results very poor efficiency.

Without knowing your circuit, I could say that 20% efficiency is easy to achieve if you chose right topology and optimize CP circuit and clock drive buffer.

Hope it helps !
 

IMHO, a single voltage doubler can do your job very well.

If the output voltage do not need to be very stable, try to use pulse skipping to regulate your charge pump.
 

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