Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Advantages of SystemVerilog compared to NCVerilog ???

Status
Not open for further replies.
B

Bulma

Junior Member level 2
Joined
Sep 27, 2006
Messages
21
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,419
I'm doing some research on choosing another simulation tool than NCVerilog. And SystemVerilog seems to have some stronger features than Verilog ... Anyone here used to use both of them can share some experiences here ??? SV is deserved to purchase ???

Thanks in advance !
 

SV is not a simulator,it is an advanced feature of Verilog.
Which can be used for System level design,Synthesisable RTL design and
can be used for Verification to interface C to ur Verilog or SV code.

Verilog95 ---> Verilog 2001 ----> SystemVerilog.
So any simulator which u are working earlier(Modelsim or NcVerilog or VCS)
will be ok,provided u use the latest versions of those simulators.
Only latest versions supports SV.
 

samuraign said:
SV is not a simulator,it is an advanced feature of Verilog.
Verilog95 ---> Verilog 2001 ----> SystemVerilog.
Click to expand...

Actually, there was also a Verilog-2005!

Verilog-95 -> 2001 -> 2005 -> Systemverilog 1800-2005

IEEE Systemverilog 1800-2005 is actually a superset of Verilog-2005 (which has some bugfixes/clarifications for Verilog-2001.)
 

SystemVerilog is an language which is most usually used for verification today.
Some syntax of SystemVerilog can't used when use ncverilog simulator.
VCS is another good choise when choose simulator
 

learnbydo said:
Some syntax of SystemVerilog can't used when use ncverilog simulator.
Click to expand...


May I know few examples where NcVerilog fails.
 

I have used them, SV is no doubt more powerful than verilog
Sumit
 

one edition of NC-sim, ncsc simulator of cadence, can simulate mixed verilog-system verilog designs.
 

Well NC is a very powerfuland versatile tool but dosent support complete accellera SV LRM.VCS supports more constructs.
Sumit
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top