LO buffer influence on phase noise

I have made RF LO with some PLL and VCO (+loop filter). The output of the synthesizer is about 0 dBm. I want to buffer it up to +17 dBm for passive mixer. Does anyone know how does the amplifier affects the phase noise? Any references?

Thanks in advance

Hi
It depends on bufer linearity -
Nonlinear circuit has Am to pm conversion effect and produce phase noise

You can simulate this (using ADS for ex) when you will design bufer

Usually with passive mixers the LO buffer is ran in saturation in order to get the best performance from the mixer. In saturation the buffer is very non-linear giving almost square wave output... so wonder what kind of effect this might have. Does anyone know a good reference to this (book or so, where this issue would be described?)

Every physical component influences the phase noise..
More or less

The saturated LO buffers used in passive mixer ICs degrade the wideband SNR of the filtered low-level input. Practical IC LO large-signal buffer amplifiers must not degrade this ratio to below –155 dBc/Hz in order to meet system requirements.

Hi, victoriya,

you should make clear at what offset the phase noise is?

The simple answer is that the phase noise is additive. That is your phase noise is the, phase noise of your synthesizer added to the residual phase noise of your buffer amp.

The phase noise of your buffer amp probably will degrade a little if driven hard, expecially if it is a FET amplifier. The phase noise of the amplifier will generally be too low to worry about. THis is usually true, unless you care about very close to the carrier noise (where the buffer amp might add in some 1/f noise), or if you are driving the buffer amp with a switching power supply and incur some sidebands.

In one respect, driving the amplifier hard will push it into a region where it does not have much am to pm conversion, so little of the synthesizer's AM noise will get converted to PM noise.

There is a case that the residual noise from amplifier (any active device) limits the phase noise floor at high offset frequency.
Though I'm not sure your end application, I think it will be OK when the integrated phase noise up to your target offset frequency is lower than the design goal.

FYI.
for your PLL development and evaluation.
"Boosting PLL Design Efficiency From free-running VCO characterizations to closed-loop PLL evaluations"
**broken link removed**

Here's the product web-site that introduced on above application note.
**broken link removed**