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When do you do parasitic extraction in design flow of SoC?

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chviswanadh

chviswanadh

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Hello,

I want to know where exatly in the design flow of an SOC does this parasitic extraction come into picture.

Please reply back with the best tools for parasitic extraction.

Thanks
chviswanadh
 

Re: parasitic extraction

hi,
Parasitic extraction comes after the DRC and LVS have been performed on the layout.
After this the post layout simulations areperformed on the netlist with extracted parasitic.

thanks
sarfraz
 

parasitic extraction

after LVS and DRC finished, you can use star-RC or DRACULE get the parasitic extraction.

but this is up to the speed you want to design. if this is not in high speed, it is not necessary to exctract the parasistic
 

Re: parasitic extraction

The Post layout extraction flow is aimed to provide spice transistor flat netlist back annotated with parasitic C’s and R’s extracted on interconnections. This flow is based on for exemple Calibre-StarRCXT tools.
RCmodels represent the analytical models used on the fly by starRCXT to compute the parasitic resistances and capacitances. RCmodels computation is based on the interconnect stack parameters described in the DRM (Design Rule Manual)
:|
 

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