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free SystemVerilog tools

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Mike_D

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Are there any free tools that support SystemVerilog? I'm looking into CAD tools and design methods at work (luckily starting with pretty much a blank slate), and at least for verification SystemVerilog seems to do just about everything I'm looking for (constrained random, assertions, etc).

I could get an eval copy of Questa or Aldec, but since it's for such a short period of time I want to get a better feel for the language first, so I can eval the tool not the langauge itself. I'm not 100% sure I want to take us that route yet, and the cost difference is huge.

Thanks,
Mike
 

Well, I was looking for free (at least as in beer, if not F/OSS). And Questa is what Mentor calls their high end version of ModelSim now, ModelSim SE does not have full support for SystemVerilog testbenches or assertions.
 

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