Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Porting a SERDES app from Xilinx to Lattice

Status
Not open for further replies.
E

Elephantus

Junior Member level 3
Joined
Jul 11, 2005
Messages
31
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,627
I am interconnecting two FPGA's over LVDS where SERDES modules are used on both ends.

The 7:1 SERDES modules are provided by Xilinx, described in the Xilinx application note xapp485. The clock is not embedded in the data but is transmitted separately with a reduced rate and reconstructed on the receiving end.

I would need to implement these SERDES modules on Lattice XP10 FPGAs. Has anyone tried implementing a 7:1 SERDES on a Lattice XP, or tried to port the Xilinx solution before?

I would appreciate any advice or help.
 

Hi,

Lattice just ported a 7:1 reference design on their website. Maybe this can help the process. But it uses a ECP2 as device.
On the other hand, what I/O speeds do you have in mind? Don't forget that the Xilinx design might use unique structures that need to be removed/converted to Lattice like structures. If I'm not mistaken, there is a guideline that comes with Lattice's software explaining what to look for.

Regards,

L
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top