sophiefans
Member level 3
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PURPOSE
This is a document which provides necessary information on the topological layout rules to generatemasks for Chartered Fab2’s 0.35um ANALOG & LOGIC, salicide and polycide, baseline and dual gate(3.3V/5V) , retrograde-well, five-layer, four- layer, three-layer or two-layer metal technologies. Flexible
plug-in analog modules include high/low sheet rho poly resistors, MiM capacitor, interpoly capacitor andmulti low Vt transistors.
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Chartered Semiconductor Manufacturing 0.35 μm CMOS process employs 3.3V or 3.3V/5V, two, three ,four, five-layer-metal digital technology. Not all of these layers are drawn directly. Therefore it is important to define properly 。
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The words above is copied from Design rule of Charter. I am just wandering what the "dual gate" mean?
1、there is only one type voltage on chip, 3.3v or 5v
2、there are two type voltage on chip, 3.3v and 5v
Which one do you think?
PURPOSE
This is a document which provides necessary information on the topological layout rules to generatemasks for Chartered Fab2’s 0.35um ANALOG & LOGIC, salicide and polycide, baseline and dual gate(3.3V/5V) , retrograde-well, five-layer, four- layer, three-layer or two-layer metal technologies. Flexible
plug-in analog modules include high/low sheet rho poly resistors, MiM capacitor, interpoly capacitor andmulti low Vt transistors.
---------------------------------
Chartered Semiconductor Manufacturing 0.35 μm CMOS process employs 3.3V or 3.3V/5V, two, three ,four, five-layer-metal digital technology. Not all of these layers are drawn directly. Therefore it is important to define properly 。
---------------------------------
The words above is copied from Design rule of Charter. I am just wandering what the "dual gate" mean?
1、there is only one type voltage on chip, 3.3v or 5v
2、there are two type voltage on chip, 3.3v and 5v
Which one do you think?