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How to convert Asynchronous Set/Reset in FF to Synchronous one?

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satiah

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Hi..

I want know if there is any way to convert Asynchronous Set/Reset in FF to Synchronous. Not the HDL code. Asyn set/Reset FF + Additional Hard ware.

I have One way Register the Set/Reset signal Is there any other way...

Thanks
 

Asyn Set/Reset

do u use standard cell? or draw the schematic by yourself? if u use standard cell, you can replace the cell
 

Re: Asyn Set/Reset

Hi..

its a schmatic.

Added after 3 minutes:

for more clarity..

these asyn FF alredy Preset in FPGA. if i use another FF to synchronize my set/reset signal its waste of my resources so i am lookig for fully opimized hardware for synchronize my signal..
 

Re: Asyn Set/Reset

u can have two consecutive flip flops
with one reset connected to both of their resets
and one clock to both of their clocks
and the output from the second flip flop will be a synchronous reset
 

Re: Asyn Set/Reset

The change is costly.
 

Re: Asyn Set/Reset

Hi salma..

what i understood if i am not wrong from ur reply is..
its FF connected back to back(like double synchronization circuit used to avoid the metastability) and having same reset and clock output is the synchronized reset. please explain me how this synchronize the reset...
 

Re: Asyn Set/Reset

It is description a asynchronize set/reset on Verilog (DFF)

always @(posedge Set or posedge Reset or posedge Clk)
if (Reset)
Q=0;
else if (Set)
Q=1;
else
Q=D

It is description a synchronize set/reset on Verilog (DFF)

always @(posedge Clk)
if (Reset)
Q=0;
else if (Set)
Q=1;
else
Q=D
 

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