negative slack after scan insertion

slack (violated)

hi all:

I got hold time violation after scan insertion.

And all of the violation path all start from the scan_enable port SE.

What should I deal with that?

below is part of the violation report

thanks

-------------------------------------------------------------------------------------
Startpoint: SE (input port)
Endpoint: s4top/mulinst/mulinst/SUB_out_reg_0_0
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Des/Clust/Port Wire Load Model Library
------------------------------------------------
fft_8k tsmc18_wl10 slow

Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 f
SE (in) 0.00 # 0.00 f
s4top/mulinst/mulinst/SUB_out_reg_0_0/SE (SDFFXL) 0.00 # 0.00 f
data arrival time 0.00

clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 3.00 3.00
s4top/mulinst/mulinst/SUB_out_reg_0_0/CK (SDFFXL) 0.00 3.00 r
library hold time -0.10 2.90
data required time 2.90
--------------------------------------------------------------------------
data required time 2.90
data arrival time 0.00
--------------------------------------------------------------------------
slack (VIOLATED) -2.90


Startpoint: SE (input port)
Endpoint: s4top/mulinst/mulinst/SUB_out_reg_1_0
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Des/Clust/Port Wire Load Model Library
------------------------------------------------
fft_8k tsmc18_wl10 slow

Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 f
SE (in) 0.00 # 0.00 f
s4top/mulinst/mulinst/SUB_out_reg_1_0/SE (SDFFXL) 0.00 # 0.00 f
data arrival time 0.00

clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 3.00 3.00
s4top/mulinst/mulinst/SUB_out_reg_1_0/CK (SDFFXL) 0.00 3.00 r
library hold time -0.10 2.90
data required time 2.90
--------------------------------------------------------------------------
data required time 2.90
data arrival time 0.00
--------------------------------------------------------------------------
slack (VIOLATED) -2.90


Startpoint: SE (input port)
Endpoint: s1top/BFa/INB_I_REG_reg_1_0
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Des/Clust/Port Wire Load Model Library
------------------------------------------------
fft_8k tsmc18_wl10 slow

Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
SE (in) 0.00 # 0.00 r
s1top/c4k/U444/Y (OR2X1) 0.23 # 0.23 r
s1top/c4k/ram_ctrl1_U2/Y (TBUFX12) 0.19 0.41 r
s1top/c4k/U186/Y (INVX1) 0.09 0.50 f
s1top/c4k/U185/Y (OAI22X1) 0.58 1.08 r
s1top/BFa/INB_I_REG_reg_1_0/D (SDFFHQX1) 0.00 1.08 r
data arrival time 1.08

clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 3.00 3.00
s1top/BFa/INB_I_REG_reg_1_0/CK (SDFFHQX1) 0.00 3.00 r
library hold time -0.22 2.78
data required time 2.78
--------------------------------------------------------------------------
data required time 2.78
data arrival time -1.08
--------------------------------------------------------------------------
slack (VIOLATED) -1.69


Startpoint: SE (input port)
Endpoint: s1top/BFa/INB_I_REG_reg_2_0
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Des/Clust/Port Wire Load Model Library
------------------------------------------------
fft_8k tsmc18_wl10 slow

Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
SE (in) 0.00 # 0.00 r
s1top/c4k/U443/Y (OR2X1) 0.23 # 0.23 r
s1top/c4k/ram_ctrl2_U2/Y (TBUFX12) 0.19 0.41 r
s1top/c4k/U202/Y (INVX1) 0.09 0.50 f
s1top/c4k/U201/Y (OAI22X1) 0.58 1.08 r
s1top/BFa/INB_I_REG_reg_2_0/D (SDFFHQX1) 0.00 1.08 r
data arrival time 1.08

clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 3.00 3.00
s1top/BFa/INB_I_REG_reg_2_0/CK (SDFFHQX1) 0.00 3.00 r
library hold time -0.22 2.78
data required time 2.78
--------------------------------------------------------------------------
data required time 2.78
data arrival time -1.08
--------------------------------------------------------------------------
slack (VIOLATED) -1.69

Startpoint: SE (input port)
Endpoint: s12top/mulinst/mulinst/Re_out_reg_18_0
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Des/Clust/Port Wire Load Model Library
------------------------------------------------
fft_8k tsmc18_wl10 slow

Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
SE (in) 0.00 # 0.00 r
s12top/mulinst/mulinst/Re_out_reg_18_0/SE (SDFFHQX1)
0.00 # 0.00 r
data arrival time 0.00

clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 3.00 3.00
s12top/mulinst/mulinst/Re_out_reg_18_0/CK (SDFFHQX1)
0.00 3.00 r
library hold time -0.15 2.85
data required time 2.85
--------------------------------------------------------------------------
data required time 2.85
data arrival time 0.00
--------------------------------------------------------------------------
slack (VIOLATED) -2.85


Startpoint: SE (input port)
Endpoint: s12top/mulinst/mulinst/Re_out_reg_19_0
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Des/Clust/Port Wire Load Model Library
------------------------------------------------
fft_8k tsmc18_wl10 slow

Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
SE (in) 0.00 # 0.00 r
s12top/mulinst/mulinst/Re_out_reg_19_0/SE (SDFFHQX1)
0.00 # 0.00 r
data arrival time 0.00

clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 3.00 3.00
s12top/mulinst/mulinst/Re_out_reg_19_0/CK (SDFFHQX1)
0.00 3.00 r
library hold time -0.15 2.85
data required time 2.85
--------------------------------------------------------------------------
data required time 2.85
data arrival time 0.00
--------------------------------------------------------------------------
slack (VIOLATED) -2.85


Startpoint: SE (input port)
Endpoint: s12top/mulinst/mulinst/Re_out_reg_20_0
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Des/Clust/Port Wire Load Model Library
------------------------------------------------
fft_8k tsmc18_wl10 slow

Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
SE (in) 0.00 # 0.00 r
s12top/mulinst/mulinst/Re_out_reg_20_0/SE (SDFFHQX1)
0.00 # 0.00 r
data arrival time 0.00

clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 3.00 3.00
s12top/mulinst/mulinst/Re_out_reg_20_0/CK (SDFFHQX1)
0.00 3.00 r
library hold time -0.15 2.85
data required time 2.85
--------------------------------------------------------------------------
data required time 2.85
data arrival time 0.00
--------------------------------------------------------------------------
slack (VIOLATED) -2.85


Startpoint: SE (input port)
Endpoint: s12top/mulinst/mulinst/Re_out_reg_21_0
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Des/Clust/Port Wire Load Model Library
------------------------------------------------
fft_8k tsmc18_wl10 slow

Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
SE (in) 0.00 # 0.00 r
s12top/mulinst/mulinst/Re_out_reg_21_0/SE (SDFFHQX1)
0.00 # 0.00 r
data arrival time 0.00

clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 3.00 3.00
s12top/mulinst/mulinst/Re_out_reg_21_0/CK (SDFFHQX1)
0.00 3.00 r
library hold time -0.15 2.85
data required time 2.85
--------------------------------------------------------------------------
data required time 2.85
data arrival time 0.00
--------------------------------------------------------------------------
slack (VIOLATED) -2.85

slack scan

Check your constraints such as upon clock network delay and input external delay.

tsmc18_wl10

you can fix it after p&r!!

negative slack

I think those are false path , don't need to fix it.
When your chip work the scan_enable will tie to high or low and will not change .
And the scan_enable signal don't need use clock to catch, it is async with clock.

Hi zgene,

I think the design does not have pads.
The current state of the design is before P&R so the I2C volation will be removed after the p&R and pad insertion.I think, i have given u the answer.

regards
Ramesh.S

Why do you need to check the scan_enable signal's hold time issue? It is not related to any clock! Am I right?

1st, is this a pre-CTS report?
if its before clock-tree synthesis the tool recognizes SE as a high fan out port and it will not buffer it.

2nd, are these reports intended to be in functional-mode or scan-mode?
make sure you set the right case analysis before reporting