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What is the best Power Analysis tool?

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cdic

cdic

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Hi, All
What is the best Power Analysis tool for Full Chip Analysis(IC design)? any comment will be appreciate.

Thank you in advance
cdic
 

Maybe Synopsys's Power Compiler?
It's integrated in Synosys DC package.
 

If you want the power analysis for Xilinx FPGA, XPower tool is there in ISE 4.1i.
simon2kk
 

power compiler is just gate level optimize
tool. Actually design power from synposys
is gate level analysis tool.
For more accuracy, the powermail or hsim
could do transistor level analysis.
 

Yeah, Transitor Level, Full chip Power analysis is just what I prefered. PowerMill took me too much time to get the result, so how about other tools? any comment will be appreciate.
 

Power Compiler & PowerMill are tools for different purpose. Power Compiler is the "synthesis" tool which try to minimize transaction on netlist based on some preliminary test vectors. Power Mill is the real transistor level power "analysis" tool based on real test vectors. If you are the designer with cell base technology (you have no idea of inside within the cells), Power Compiler can help you to optimize your netlist for power. If you are designer with full custom technology (you can access the spice netist of cells or even if you create them by yourself), Power Mill is suitable for you. So far, as I know, Power Mill is the best power "analysis" tool which get the best trade off between accuracy and computing resource.
 

It depends on what you mean by power analysis....

Power grid: There is a tool from IOTA which can help you analyze your power grid IR drops and electromigration. You need to define the activity level of your ciruits.

System Level: You can use Star-RCXT from Avanti. They use to offer Star-Power as a standalone tool but now it has been incorporated into Star-RCXT. For this tool, you need to define the activity level of your circuits.

Gate level: You can use Synopsys Prime Power or Power Compiler for this. This requires you to carefully characterize your library.

Transistor level: Powermill is obsolete. The tool from Synopsys for this is called Nanosim. Nassda HSIM also has some power analysis features. You can also use Hspice.
 

Thanks Jaz for your comment, I need to do the power grid analysis and the transistor level, full chip power analysis.
so how about simplex tool voltage strom?
 

HSIM is ok. You may add parasitics as a DSPF and digital vectors as a stimuli.
There is some power grid analysis in FirstEncounter, also CADENCE
pwrAnalysis may be used, but this tool is not very friendly. Last but
not least, the library must be well characterized for the current consumption and not for the energy (e.g. Artisan uses unfortunately "energy")
 

simplex VoltageStorm is the best choice!
 

I have powermil & hsim. I like hsim.
 

Up to date, there are so far from synopsys and cadence can provide good
power analysis in static and dynamic

From RTL level, you can use power compiler to estimate ur module-to-module
power consumption
From gate level, you can use primepower to estimate the real gate level power
consumption with the provision of synopsys libraries
From transistor level, dynamically, you can use nanosim/hsim to do fast extraction on power consumption and use VCS with nanosim to do mixed mode power analysis especially on leakage or sleep mode current consumption which is so far the best and fastest mixed mode tool i have ever use the best
From PR online level, u can use Astro Rail to do static IR drop analysis or use voltagestorm to do this job
 

Have u heard about any tool called power theatre, which is used for the power analysis.
 

Yes. Sequence's PowerTheater is also a great power analysis tool.

One of its good feature is it can model the clock tree networks properly before CTS.
Please refer to the following link for more detail.
**broken link removed**
 

Power Theatre(full-chip power analysis) and Cool Time(dynamic voltage drop analysis) from Sequence Designs are very good solutions to do power analysis.
 

Xilinx's XPower is very easy to use if you have an FPGA design or if you are prototyping a design on an FGPA. You can get the power by doing the foloowing.

- Setup a testbench using the Bencher built into Xilinx or write up your own testbench.

- Run the post-layout simaulation with the ModelSim from within Xilinx. This will generate a .wlf file in your project folder. The newer ModelSim (5.8 and beyond I think) come with a wlf2vcd tool to convert the .wlf to .vcd file.

- You will need the .vcd file generated by the tool to put into XPower. Depending on the size ofyour design it will load all the values in faster or slower, no surprises there.

From here on you can vary the Vdd and the clocking frequencies to find the differences in dynamic (the figure you would be interested in) and quiescient power (this is the amount of power that the FPGA uses no matter what your design does).

This might give an idea of what major changes in your design will do to your power consumption. It might be faster than some of the other tools of course depending on the size of the design. It might work out to be cheaper if you dont have access to ASIC design/verification tools.
 

I've heard NanoSim is the latest power analysis tool from synopsys. They claim it is 100 times faster than Hspice with accuracy of 2-4% of Hspice. It is also capable of simulation of SOC design with embedded RAM and ROM block.
Have anyone worked with this tool? Can you give us a brif how much this claim is true?
Does cadence have any tools like powermill or nanosim?

Regards
 

Maybe,some small software is your choice. for example: Huada's Zeni (China)
 

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