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Do some one use Assertion Based Verification?

do you use Assertion in your verification?

  • no,never

    Votes: 0 0.0%

  • yes,use PSL

    Votes: 0 0.0%

  • yes,use SVA

    Votes: 0 0.0%
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I heared it many times,and it can improve productive,can some give me any suggestion?
is it really action?and the learn curve is sharp?
 

I honestly don't know..

but tommorow aldec system verilog online seminar.. so we'll see how that goes..

but i've only worked at 0.5um.. so verilog benchs were good enough..

jelydonut
 

Hi ,

Assertion based verification is one of the good concept for module level verification .
people in industry reailized the importance of the same . as it is won't regquire any simulation it is really good .

Thanks & Regards
yln
 

Yep! Assertions can save u a lot of debugging time!
cheers
 

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