Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to change the code if I use if-else statements and have timing problems?

Status
Not open for further replies.
H

hariharan4000

Junior Member level 1
Joined
Dec 4, 2005
Messages
15
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,422
Hi
i had a question in verilog in an interview. ie..

if u r using nested if-else statements in your code and u find some timing problems.
In that case how will u change your code (problem is with the nested if-else).

Plz get me the solution..

haran
 

Re: verilog-- query

change the nested if elsif in a clocked process. or try using parallel case if logic permits.
 

verilog-- query

"if-else" will be synthesized to priority level circuit;
on the contrary , "case" will be synthesized to parallel circuit.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top