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why Multi vt ? relation with leakage current

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manivannanrm

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how multi threshold voltage cells reduces leakage current in an design?
I read that high vt cells used for noncritical paths and low vt cells for critical paths why?
tnx in advance
 

hello manivannam,

MTCMOS tech is the latest one to reduce leakage power , there many papers and publications related to this topic. well in short i can give u the following points ,

1) In MTCMOS tech. a cluster of cellls are connected to through high Vt Nmos, we can say this as power gating
2) a high vt NMOS r PMOS can be inserted in a non critcal path.
3) the performance of the ckt may change if this is implemented in critical path as it takes soem time to turn on.

jan rabeay books explains very clear abt this .. and many IEEE papers by anantha chandrakasan ..

so u if u need any papers let me know .. i am presently working with leakage power ..

suresh
 
as far as i know, low-vt devices work faster but they consume more power due to subthreshold current leakage. high-vt transistors reduces this leakage significantly but its delay time will be longer than low-vt devices.

that is why low-vt device are used in critical path (needs to be fast), whereas high-vt transistors can be employed on non-critical path where speed is not a concern to save power.
 
Dear Mani,
The thinkness of gate oxide (or the dielectric constant) and the substrate voltage has a direct impact over the Vt of a transistor.
When the oxide layer is thin, Vt is less; delay is less but the cell can easily pick up the noise.
When Vt is high, there is less power consumption and high delay.
 

go through the attchment u can get good idea
 

Hi suresh
can u give me some links to papers on leakage reduction with MTCMOS. I want to know how stacking multiple vt transistors can reduce leakage like stacking a low vt device on a high vt device??

Please send me link to some papers.

Thanks
Singu
 

hello singu

i am sending u some docs of IEEE, i hpe these are useful for u...


suresh
 

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