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LVS issue with extracting info about multiple gate transistors from the layout

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khorlipmin

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I am using AMS HIT-KIT, I am not sure whether this problem is design kit specific. I defined multiple gate transistors in schematic and layout (stripes). so if you observe it in the netlist, a 4-gate nmos will have m=4.0 associated with it.
However I failed to extract this information through the layout. It always extracted into four transistors all having m=1.0 thus making my LVS to fail.
The only solution so far is to change the extracted netlist to m=4.0 and the LVS will pass.
This is frustrating for large circuit. Any idea what did I did wrong? thanks very much.
 

avoid m issues is not to use multiplicity

What LVS tools do you use (Diva, Dracula Calibre)?
For Dracula there should be LVSCHK option in command file that allow smash or unsmash parallel devices.
 

diva lvs permute device

I am using DIVA. Is there a similar option? I could not find one so far... or maybe i missed out?
 

Re: LVS issue

I use Diva for Layout and Virtuoso schematic editor for schematic. This doesn't happen to me. I guess in the device properties window (in schematic) u will have a parameter namely " No of Gates". U put 4 out there. So for a 40um device it automatically will employ 4 mos with 10um each. That m=4.0 may be misleading. U can try it out.

sankudey
 

LVS issue

Your divaLVS file doesn't have a parallel permute rule for mosfets, or it doesn't handle parameter "m". Please modify divaLVS.rul.
 

LVS issue

Since I do not have the permission to modify the file, does it mean that the only choice then would be to modify the layout netlist?
thanks hughes
 

LVS issue

Why don't you have the permission? If it is owned by another user, you can make a copy of it and modify the copy.

Modify the layout netlist is not a good idea.
 

LVS issue

I guess you should try to use what sakundey proposed.
I do not know how AMS but some PDKs require special lauyer for m>1 devices.
I also recommend to look at the manual for Ayour design kit and send email to AMS - they are usualy quite responsive.
 

LVS issue

yes that is a good idea, i hope they will be helpful. will contact AMS now.
 

Re: LVS issue

hi everybody!!

I'm faced to the same problem with diva about the handling of M factor do anybody know finally howw to resolve this? Thanks
 

LVS issue

The easiest way to avoid "m" issues is not to use multiplicity. TSMC has sometimes similar issues in PDK.

I recommend to use "bus" representation instead.
By that I mean something like this: PMOS1[1:6]
which means 6 times the same PMOS in parallel - so Wtot = 6x Wpmos

Also I believe AMS hitkits have a special LVS setups to use - use their documentation. In MentorGraphics they had a blue menu button you had to select befor any LVS run
 

Re: LVS issue

hi Teddy!!
thanks for your response. by "bus" representation PMOS1[1:6] do you mean to place in the schematic 6 transistors in parallel? for a very large circuit, this is not very convenient. Doyou know another way more efficient??
 

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