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About line regulation of LDO

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jefferson

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ldo line regulation

Hi all,
A problem I meet is that my LDO has a bad line regulation.
As Vin increases from 2.5V to 6V,Vout decreases by about 40mV,too big,Ithink.
Is the duty of error amplifier's offset voltage?

for it's already a chip,I can't measure the +/- point of EA.

Any reply would be apprecaited.
 

line regulation in %/v

Hi Jefferson,

That is strange because in the regulation mode, the Vout should also rise when Vin increases. I think that is a reliability problem than a design problem. Are you sure that your pass transistor is reliable for that voltages. Offset voltage of the Opamp is a function of its DC gain, which i suppose will not get effected so much when the VDDs increase.

Anyways on the number 40mV, I think that it is a high number. A good line regulation should be less than 0.5%
 

ldo line regulation

I don't think the Vout always rise when Vin increases, it will be determined your EA achitecture, it is a complex problem such as channel length modulation,offset and so on.
 

load regulation and line regulation

are you sure reference is good? I think it also depend on this .
 

line regulation ldo

The output should not change with the input for an ideal regulator -- that is why it is called a 'regulator' anyway.

The limited line regulation can come from different sources: bandgap voltage (or reference voltage) line regulation, error amplifier finite DC gain (but NOT the offset), etc.

You may need to check it more thoroughly with the design if it is available to you.
 

bad line regulation

I'm sure bandgap is good.
But how can the Vout goes down when VDD increase? I can't understand.
Even if it is the reason of EA's offset,or channel length modulation,I think Vout should increase with VDD.
besides,the DC gain of the whole loop is about 70dB. maybe enough for a LDO.
 

line regulation error

Check if this LDO is providing more than sufficient current to all the components.
Then check that your LDO Cin >> Cout.
Any inductive devices after LDO?
Any polarised caps wrongly placed at LDO load/output?
 

line regulation equation

TO SkyHigh:
Do you think how does the supply current influence the line regulation?
There isn't any inductive deices after the LDO except its pins. Caps used are all 1u ceramic caps.
 

jefferson said:
I'm sure bandgap is good.
But how can the Vout goes down when VDD increase? I can't understand.
Even if it is the reason of EA's offset,or channel length modulation,I think Vout should increase with VDD.
besides,the DC gain of the whole loop is about 70dB. maybe enough for a LDO.
Click to expand...

Generally, Line regulation is : ΔVout/ΔVin≈gmp*rop/(A*β)+ΔVref/(β*ΔVin)
please check every factors to understand, good luck!
 

smartdream said:
jefferson said:
I'm sure bandgap is good.
But how can the Vout goes down when VDD increase? I can't understand.
Even if it is the reason of EA's offset,or channel length modulation,I think Vout should increase with VDD.
besides,the DC gain of the whole loop is about 70dB. maybe enough for a LDO.
Click to expand...

Generally, Line regulation is : ΔVout/ΔVin≈gmp*rop/(A*β)+ΔVref/(β*ΔVin)
please check every factors to understand, good luck!
Click to expand...

I think your equation is about LDO use bipolar device such as pnp transister as the pass element . Still I don't understand what does gmp*rop stand for.
I use a PMOS as the pass element,which I think the line regulation should be 1/[(Rds+Rl)*gm*A ]+ΔVref/(gm*ΔVin).isn't it? If calculated in this way,the line regulation would be less than 1mV for the high gain of the error amplifier?
thanks.
 

I am also want to know what could make the line regulation become bad? just the EA's gain? Any other main fators?
 

If Vout decreases when Vin is increased, this can be a stability problem.
It may cause oscillation.
By the way, Jefferson did not mention Vout voltage. Did he?
Please provide more information on the circuit.
Regards,
 

shwoo said:
If Vout decreases when Vin is increased, this can be a stability problem.
It may cause oscillation.
By the way, Jefferson did not mention Vout voltage. Did he?
Please provide more information on the circuit.
Regards,
Click to expand...

the oscillation can be detected by the oscilloscope. however, when oscillating, the vout is far away from the normal value.
 

shwoo said:
If Vout decreases when Vin is increased, this can be a stability problem.
It may cause oscillation.
By the way, Jefferson did not mention Vout voltage. Did he?
Please provide more information on the circuit.
Regards,
Click to expand...

It's not oscillation as I observed on the oscilloscope, the Vout voltage just decreases by about 30-40mV as Vin increases .The load regulation is no good too.
Bye the way,Vout is 1.8v, gain of EA is 65dB simulated.pass device is PMOS with W/L=35000.Vref is about 1V.
 

Maybe you should simulate all the regulator loop gain but not just the EA, if the reference voltage is right, maybe the loop has problem.
 

I think the PSR of votage reference should be checked.
 

As far as I am concerned Vout always rise when Vin increases.
 

Perhaps your EA gain is changed because some transistors are not in saturation region. You should check your bias circuit to confirm it
 

jefferson said:
smartdream said:
jefferson said:
I'm sure bandgap is good.
But how can the Vout goes down when VDD increase? I can't understand.
Even if it is the reason of EA's offset,or channel length modulation,I think Vout should increase with VDD.
besides,the DC gain of the whole loop is about 70dB. maybe enough for a LDO.
Click to expand...

Generally, Line regulation is : ΔVout/ΔVin≈gmp*rop/(A*β)+ΔVref/(β*ΔVin)
please check every factors to understand, good luck!
Click to expand...

I think your equation is about LDO use bipolar device such as pnp transister as the pass element . Still I don't understand what does gmp*rop stand for.
I use a PMOS as the pass element,which I think the line regulation should be 1/[(Rds+Rl)*gm*A ]+ΔVref/(gm*ΔVin).isn't it? If calculated in this way,the line regulation would be less than 1mV for the high gain of the error amplifier?
thanks.
Click to expand...
I think when you use a PMOS as the pass element, which I think the line regulation should be Vout/(A*Vref)+ΔVref*Vout/(A*Vref). If calculated in this way, the line regulation would be about 4mV for your circuit. And the output voltage will increase when the input voltage increase.Maybe something is wrong with your EA.

Added after 1 minutes:

Maybe you should do FIB to test your EA.
 

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