listing all ifdef parameters used in design

HI,
I need to list all the ifdef parameters used in my Design. Along with this list I need to know if these parameters are defined in some include file or not?
I have a TCL script to do it but I am facing problems like:
1. If include file has code:

'ifdef FIRST_CONDITION
define SECOND_CONDITION
define THIRD_CONDITION
'endif

Now if Parameter FIRST_CONDITION is not defined any where then SECOND and THIRD CONDITION should not be defined but the TCL based script works on text parsing and it can not check this condition.
Most important is I can not spend time on modifying this script.

2. My TCL script can not take care of 'undef

My Questions:
1. Can any one provide script which can do this job properly?
2. Is there any EDA tool which can report this?

Help appriciated.

Regards,
JItendra

Commercial EDA tools should be able to do this. However, since these are pre-processor directives, it is possible that it in non-trivial to get that list. One tool that I can think of is a Lint tool such as Leda from Synopsys. They usually don't optimize your design and hence might preserve these.

Other options are:

1. There is a VPP - Verilog pre-processor, opensource in web, may be you can hack it to get this.
2. Icarus/Cver are opensource Verilog simulators - you may be able to hack them to do this for you.

Let me know how it goes.
Ajeetha, CVC
www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 https://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar