Behavioral modelling for mixed signal designs

Hello everyone,

I want to know abt behavioral modelling of analog circuits in mixed signal designs.

Are there any levels of behavioral modelling as spice?? If so what are the levels and where do they come in use?

please give me some inputs regarding this.

Thanks
Kasi

This docs may help u...


1.
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Verilog-A and Verilog-AMS provides a new dimension in modeling andsimulation

Miller, I. Cassagnes, T.
Motorola ESD Europe, Chandler, AZ;

This paper appears in: Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on
Publication Date: 2000
On page(s): C49/1-C49/6
Meeting Date: 03/15/2000 - 03/17/2000
Location: Cancun, Mexico
ISBN: 0-7803-5766-3
References Cited: 2
INSPEC Accession Number: 6783688
Digital Object Identifier: 10.1109/ICCDCS.2000.869811
Posted online: 2002-08-06 23:16:11.0




Abstract
Verilog-A provides a new dimension in modeling, design and simulation capability for analog and mixed signal electronic systems. Previously, analog simulation has been based upon Spice, which is a very effective simulation environment based on primitives such as transistors, resistors, and capacitors. Digital design verification is based on a Hardware Description Language (HDL). Verilog and Verilog derivatives have been widely accepted due to their ease of use and gate level simulation capability. Verilog, which accounted for more than 60% of the HDL simulator sales in 1997, has a strong following with a host of tools that complement the language and extend the capability to verification and test. This paper presents the motivation for the Verilog-A language, an extension of Verilog to describe analog and non-electrical behavior, and illustrates the Verilog-A language via short examples and a overview of an ink jet printer ASIC support IC behavioral model


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2. Efficient testing of Analog/ Mixed Signal ICs using Verilog-A :: by Nitin Mohan....

**broken link removed**

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sankudey

Hi Sankudey,

Thanks for the reply. I couldnt access the URL that u have given.

Thanks
Kasi

See https://www.designers-guide.org. There u can download Verilog-AMS Language Reference Manual.
And verilog-a is a part of verilog-ams.
Levels of abstraction is depended from u

In spice you can model one block of your circuit with current-controlled and voltage-controlled sources and define it as a subcircuit. for example you can model an opamp with two resistors for input and output and a voltage-controlled current source. at a higher level simulink is very good. like modeling of a whole delta-sigma modulator.

hello Denis,

My doubt is how to determine what level of abstract to be used for a particular design.

thanks
kasi

When system engineer develops model, he begins from simple block models (e.g. Vout=A*Vin). Than he defines this models more precisely in order to determine block characteristics (delays, gain, etc.). After this block engineer makes schematic.