A question about MOS capacitances

mos capacitances

During these days I have been reading the book Design of Analog CMOS Integrated Circuits by Behzad Razavi, in Figure 2.30 of Chapter 2 there is a capacitance labled CGB, but I can't understand why there is a capacitance between gate and sub 'cause in my opinion CGB=CGS+CSB/CGD+CDB, can someone explain the principle of CGB for me? By the way, in Allen's book, he says there is a capacitance CDS between drain and source, can someone explain it for me, I don't understand why there exists a capacitance between D and S, this is even more difficult for me to understand.
Thank you in advance!!!

These are all parasitic capacitances in the real physical chips.
Just think about the characteristic of capacitance: if the voltage applyed changes,the amount of charge will changes.
Then on the opposite ,if the amount of charge will change with the applied voltage there is a equivalent capacitance.

Please see p84,85 in Allen's Book (Figure 3.2-6) about Cgb

and, the capacitance between Drain and Source isn't negligible at short-channel length.

Hello,

Gate-to-substrate capacitance exists, it's the capacitance of the gate poly outside channel to substrate. the gate poly extensions outside the active region will have capacitance,

As asic_ant said, you may think of MOS as four plate capacitor, all sharing charges between each other, so any change of any node voltage will affect the rest of plates. For more rigid understand of capacitance model in MOS you need a devices book, I recommend Tsividis.

aomeen said:

Hello,

Gate-to-substrate capacitance exists, it's the capacitance of the gate poly outside channel to substrate. the gate poly extensions outside the active region will have capacitance,

As asic_ant said, you may think of MOS as four plate capacitor, all sharing charges between each other, so any change of any node voltage will affect the rest of plates. For more rigid understand of capacitance model in MOS you need a devices book, I recommend Tsividis.

Click to expand...

Thank you for your post, but you know it is difficult to buy Tsividis's book here

Hi,
I think that this expression is wrong, CGB=CGS+CSB/CGD+CDB, because the gate capacitance not depend of the depletion capacitances CDB (drain to bulk JUNCTION capacitance) and CSB (source to bulk junction capacitance).
The CGB capacitance if formed basically with the series capacitances Cox and the semiconductor capacitance Cs, that is : C= 1 / [ (1/Cox) + (1/Cs) ]. In the case of two metallic capacitor, the capacitance Cox will be calculated from the dielectric permittivity and the height of the two plates, but in a MOS structure, the replacement of one metallic electrode by an semiconductor electrode cause a reduction in the total capacitance, that is, the applied potential to the dielectric is reduced by the fall of potential in the semiconductor. This reduction of charge and thus of the capacity is modelled by the addition in series of the Cs capacitance (semiconductor capacitance) who is a non linear capacitance, that is, variable with the Vg applied voltage. In accumulation (remember with VG) regimen Cs is two big resulting in CGB≈Cox (remember that the two capacitances are in series). In depletion (remember with VG) regimen, Cs is very small resulting in CGB≈0. In inversion regimen the situation is a little complex for the calculation of CGB, depending of the frequency applied to the gate CGB≈Cox or CGB≈0.
The TOTAL Gate to common (ground for a NMOS and VCC for a PMOS) capacitance is obtained by the sum of the overlap capacitance, Cox capacitance and the Cs capacitance.
In Cut-Off:
CGB(total)=Cox∙W∙ L
CGD(total)=Cox∙W∙LD
CGD(total)=Cox∙W∙LD
In Linear:
CGB(total)=0 (because CS is to big)
CGD(total)=(1/2) Cox∙W∙ L +Cox∙W∙LD
CGS(total)=(1/2) Cox∙W∙ L +Cox∙W∙LD
In saturation:
CGB(total)=0 (because CS is to big)
CGD(total)=Cox∙W∙LD
CGS(total)=(2/3) Cox∙W∙ L +Cox∙W∙LD

Best regards,
FC

qiushidaren said:

Thank you for your post, but you know it is difficult to buy Tsividis's book here

Click to expand...

No it's not , here is it

why am I not able to open the link????????

Cgb exists directly whenever the channel is not inverted.
That is in addition to the perimeter and "overhang" capacitiance mentioned elsewhere.

The small signal model for the capacitance changes depending on the bias point of the transistor.