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multiplication in verilog with value from ROM

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siva_7517

siva_7517

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Hi,
I am currently doing multiplication with 2 different value of Q which is from ROM.
Below is an example of code of top module :

top (....)
..
..
assign tmpMult_1 = $signed(A) * $signed(Q); // Q=0.7071
assign tmpMult2_1 = tmpMult_1 - ($signed(B) * $signed(Q)); // Q= -0.7071
..
..
endmodule

I have a ROM verilog code:

module rom (read_en, address, Q);
input read_en;
input [2:0] address;
output [15:0] Q;
reg [15:0] Q;
always@(posdege read_en)
begin
case (address)
1'b0 : Q <= 16'b0101101010000010 // 0.7071
1'b1 : Q <= 16'b1010010101111110 // -0.7070
endcase
endmodule


How can instantiate this code to top module?
thanks in advance
 

Maybe you would try to clock the outputs of ROM for different inputs so that you can re-use the ROM module for two Q values at the same time.
 

siva_7517 said:
Hi,
I am currently doing multiplication with 2 different value of Q which is from ROM.
Below is an example of code of top module :

top (....)
..
..
assign tmpMult_1 = $signed(A) * $signed(Q); // Q=0.7071
assign tmpMult2_1 = tmpMult_1 - ($signed(B) * $signed(Q)); // Q= -0.7071
..
..
endmodule

I have a ROM verilog code:

module rom (read_en, address, Q);
input read_en;
input [2:0] address;
output [15:0] Q;
reg [15:0] Q;
always@(posdege read_en)
begin
case (address)
1'b0 : Q <= 16'b0101101010000010 // 0.7071
1'b1 : Q <= 16'b1010010101111110 // -0.7070
endcase
endmodule


How can instantiate this code to top module?
thanks in advance
Click to expand...


It's very simple

you'r data type in the rom module is

read_en ---- input wire type
address ---- input wire type
Q ---- output reg type


now to instantiate this module in top module declare
read_en as reg or wire type
address as reg or wire type
Q as wire type
(all the variables with same size)

and instantiate as

rom <module_name>(read_en,address,Q);

*module_name could be any character
 

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