hrkhari
Full Member level 4
Hi Guys:
I need some help in the design of the prescaler circuit for my VCO. I find many journals proposing circuit such as ILFD (Injection locked frequency divider) or a commonly used static master-slave flip-flop based frequency didivder. Based on the theory I understand the former architecture relaxes the power consumption requirement. The question is:
1. Does a frequency divider circuit needs to biased in switching mode or inversion mode?.
2. I noticed that, there is a CLK input apart from the D, /D and Q,/Q output, if my frequency of oscillation is 3.5GHz, How much does high does the CLK should oscillates?.
3. In configuring a divide two circuit from a common D master-slave flip-flop, one needs to cross couple two of this flip-flops, to tap the output from the second Q, /Q output (correct me, if it is otherwise). Does this integration require intermediate inverter connection?, Why?.
Your kind assitance is highly appreciated. Thanks in advance
Rgds
I need some help in the design of the prescaler circuit for my VCO. I find many journals proposing circuit such as ILFD (Injection locked frequency divider) or a commonly used static master-slave flip-flop based frequency didivder. Based on the theory I understand the former architecture relaxes the power consumption requirement. The question is:
1. Does a frequency divider circuit needs to biased in switching mode or inversion mode?.
2. I noticed that, there is a CLK input apart from the D, /D and Q,/Q output, if my frequency of oscillation is 3.5GHz, How much does high does the CLK should oscillates?.
3. In configuring a divide two circuit from a common D master-slave flip-flop, one needs to cross couple two of this flip-flops, to tap the output from the second Q, /Q output (correct me, if it is otherwise). Does this integration require intermediate inverter connection?, Why?.
Your kind assitance is highly appreciated. Thanks in advance
Rgds