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Yes, there is a divider in orignal 8085, however there are devices avialable from different manufacturers with higher clk frequiencies than orignal dev. and with selectable dividers. Why divider is their ..... I don't know ;-) ....
There are no divider, but internal CPU state machine requires TWO clock cycles to interpret ONE instruction word. Similary inside oryginal 8051 requires 12 clock cycles for make ONE word instruction, but there are no "divider", In Microchip PIC's there are 4 clock required for one instruction, but there are no "divider".... All of this depends from internal CPU state machine architecture.
bis
There are no divider, but internal CPU state machine requires TWO clock cycles to interpret ONE instruction word. Similary inside oryginal 8051 requires 12 clock cycles for make ONE word instruction, but there are no "divider", In Microchip PIC's there are 4 clock required for one instruction, but there are no "divider".... All of this depends from internal CPU state machine architecture.
bis
r u sure bis_?
frm what I know there is an internal clock divider in 8085 and the reason is to produce a symm waveform(one having 50% duty cycle) if the input clk is not so.
Try it yourself : take a non symm. clock and divided it by two , the output clock will be symmetrical
Added after 5 minutes:
bis_ said:
There are no divider, but internal CPU state machine requires TWO clock cycles to interpret ONE instruction word.
I think you r right here that 8085 uses two clock signals one for + edge triggering and one for negative but they r obtained by an internal inverter and has nothing to do with clock divider.
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