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Help me with interstage matching of two stage amplifier designs

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leedsuni

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i am working on the interstage matching of two stagw amplifiers design, but i cant get any useful results, my main aim is to obtain the gain flatness, ineed help !!!!

this is my disign
 

interstage match

is it an IC design or discrete level design? actually to have a gain flatness, you have to have a mismatch between source to load...its called selectively mistmatch..by doing so you get stable gain in all frequencies....
 

Re: interstage matching

MK28 said:
is it an IC design or discrete level design? actually to have a gain flatness, you have to have a mismatch between source to load...its called selectively mistmatch..by doing so you get stable gain in all frequencies....
Click to expand...



hi,
how we can have interstage match, is there any method to get the interstage match, or simply by puting L or C in the interstage.(i am talking abt IC)
thanks
 

Re: interstage matching

why not giving real problem along with actual IC no. so that someone can help u?
 

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