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Information about powerclamps in IC design

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E-goe

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Hi

Can somebody provide me with some information about powerclamps in IC design?

What is it doing,why is it needed, how to implement it

Also any papers, related chapters of E-books ...
 

Re: Powerclamp

Power Clamps allows to create a current path to discharge the power supply rails during ESD events (electro static discharge).

It limits the VDD/GND voltage to the supply value during ESD events.
 

Re: Powerclamp

powerclamp is used between vdd and vss, it provide a path for esd discharge, for mutliple power chip, there must be a power rail to rail for providing the esd discharge path.
normal , powerclamp circuit can be diode or ggnmos and rail to rail(someone call powercut )circuit can use at least two diode (anti parrallel).
 

Re: Powerclamp

P mos device can also be used as clamp based on the fact that if the gate drive is 0, it is default as on, so it can serve as a path from VDD to ground, but of course a lot of supporting circuit are required to make sure it does not impact normal circuit function.
 

Re: Powerclamp

mdcui said:
P mos device can also be used as clamp based on the fact that if the gate drive is 0, it is default as on, so it can serve as a path from VDD to ground, but of course a lot of supporting circuit are required to make sure it does not impact normal circuit function.
Click to expand...

PMOS powerclamp is also gate connected to supply type.
So it will not influence normal function during no ESD event.
　
 

Powerclamp

I think FAB can give you the Clamp circuit and layout.
 

Re: Powerclamp

Hi E-goe,

The following book has a section in chapter 4 about power clamps. You can download it here via the link. Hope that this helps you for the better understanding of power clamps.

On-Chip ESD Protection for IC - An IC Design Perspective, Albert Z. H. Wang
h**p://
 

Re: Powerclamp

powerclamp is for VDD TO VSS.and power cut is for different VDD or different VSS.
 

Re: Powerclamp

Power clamp is used for ESD protection.
There are 2 blocks, one is ESD detection block and other one is big mos transistor between power and ground and it's gate should be connected to ESD detection block.
The idea of ESD detection block is that ESD surge is faster rising time than normal power up time.
 

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