C Based Verification in VLSI

Similar threads

• K

  explanation of how to translate C code into verilog

  • Started by keikaku
  • Mar 5, 2024
  • Replies: 10

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  Looking for a communication project based on FPGA and PC and W5300

  • Started by MLSD
  • Aug 23, 2023
  • Replies: 2

  PLD, SPLD, GAL, CPLD, FPGA Design
• J

  FPGA based ATE (Automatic Test Equipment)

  • Started by jenish
  • Apr 26, 2023
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  [SOLVED] VHDL Based N-point FFT with fixed point package really slow, suggestions or improvements?

  • Started by mhmert
  • Aug 17, 2023
  • Replies: 13

  PLD, SPLD, GAL, CPLD, FPGA Design
• S

  Cannot identify inferring latches in code

  • Started by sims0702
  • Apr 12, 2024
  • Replies: 10

  PLD, SPLD, GAL, CPLD, FPGA Design