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questions on LDO's PMOS power transistor

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greenhand

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Hi,everyone :
I have some questions on the LDO's PMOS pass device .
In one Rincon-Mora 's paper , it's said that "
the maximum quiescent current was higher than expected
by simulations for the effects of the large voltage drop
across the Schottky diode on the parasitic vertical PNP
transistors inherent in the PMOS structure . This can be
improved by increasing the diode 's area or placing heavy
dopant buried layer under the PMOS"
So my first question is what the above words mean ?
My second question is how the PMOS pass device
is build in nomal CMOS technology , and from where
I can downlowd the proper PMOS power transistor's
spice model ?

Thank you forward !
 

greenhand said:
Hi,everyone :
"the maximum quiescent current was higher than expected
by simulations for the effects of the large voltage drop
across the Schottky diode on the parasitic vertical PNP
transistors inherent in the PMOS structure . This can be
improved by increasing the diode 's area or placing heavy
dopant buried layer under the PMOS"
So my first question is what the above words mean ?
Click to expand...

It's a project where pass device's threshold voltage is decreased by using schottky diode, but you won't have schottky'ies model in a standard CMOS.

greenhand said:
My second question is how the PMOS pass device
is build in nomal CMOS technology , and from where I can downlowd the proper PMOS power transistor's spice model ?
Click to expand...

Mainly it is high voltage (3.3V, 5V) transistor with huge W/L aspect ratio. It doesn't differ much from low power transistor apart from layout. The spice model you can take from MOSIS page.
 

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