Assignment MUXs in Verilog

module mux (
   // Outputs
   data_out,
   // Inputs
   output_select, saved_rx_data
   );
   input [2:0] output_select;
   input [12:0] saved_rx_data;
   output [7:0] data_out;
   
   assign data_out = ((output_select == 3'h1) * {2'b0, saved_rx_data[12:7]})
                   + ((output_select == 3'h2) * {1'b0, saved_rx_data[6:0]})
                   + ((output_select == 3'h3) * 8'h00);
endmodule // mux

module test();
   reg [2:0]            output_select;          // To mux of mux.v
   reg [12:0]           saved_rx_data;          // To mux of mux.v
   wire [7:0]           data_out;               // From mux of mux.v
   mux mux (
            // Outputs
            .data_out                   (data_out[7:0]),
            // Inputs
            .output_select              (output_select[2:0]),
            .saved_rx_data              (saved_rx_data[12:0]));
   initial begin
      $monitor ($time,,"A= %x B= %x C= %x SEL=%x Y= %x",
                {2'b0, saved_rx_data[12:7]}, {2'b0, saved_rx_data[6:0]}, 
                0, output_select, data_out);
      output_select = 0;          
      saved_rx_data[12:7] = 6'h1a;
      saved_rx_data[6:0]  = 7'h55;
      #10 output_select = 1;
      #10 output_select = 2;
      #10 output_select = 3;
      #10 $finish;
   end
endmodule // test

reg [7:0] data_out ;
always @ *
begin
   case(output_select)
   3'h1:
   begin
      data_out = {2'b0, saved_rx_data[12:7]} ;
   end
   3'h2:
   begin
      data_out = {1'b0, saved_rx_data[6:0]} ;
   end
   default:
   begin
      data_out = 8'b0 ;
   end
   endcase
end