Thomson
Full Member level 3
chip die area
hi,
does anybody have an approximate equation describing the chip/die area depending on the gate counts and ssrams or other compiled macros to estimate the die area (without IO pad) since this gross estimation will help me to decide whether the chip is pad limited or core limited.
Thanks in advance,
Thomson
hi,
does anybody have an approximate equation describing the chip/die area depending on the gate counts and ssrams or other compiled macros to estimate the die area (without IO pad) since this gross estimation will help me to decide whether the chip is pad limited or core limited.
Thanks in advance,
Thomson